In order to reduce the number of terminals and interconnection lines, many electronic circuit devices having a plurality of large scale integration (LSI) chips mounted on a circuit board include a data transfer circuit using a bi-directional bus. In such a case, a bi-directional buffer incorporated into an LSI chip and serving as an I/O circuit is connected to the bi-directional bus formed on the circuit board. The bi-directional buffer is controlled so as to stay in an input state or an output state. Thus, the bi-directional buffer has a data input function and a data output function. An output circuit formed in the bi-directional buffer includes a tri-state buffer that can control switching between an active state and an inactive state. When the output buffer enters an inactive state, the input circuit is controlled to receive a logic signal on the bi-directional bus.
The input and output voltage of a bi-directional buffer (i.e., the logical amplitude of a signal on a bi-directional bus) has been decreased in order to reduce power consumption. When a digital signal having a small logical amplitude is transferred via a bi-directional bus, the digital signal tends to be easily affected by parasitic capacitance and noise. Accordingly, in order to increase the noise immunity, it is desirable that an output voltage be set to a value having an optimal margin for an input logical threshold voltage. The optimization of the input threshold voltage and the output voltage also increases the data transfer rate and decreases the power consumption. On the other hand, the characteristics of an input and output transistor of the bi-directional buffer and the impedance of an input and output path are affected by variations in the process for manufacturing an LSI chip and a circuit board and, therefore, are changed from the design values. In addition, the optimal output voltage varies in accordance with the use environment of a manufactured electronic circuit device (in particular, the power supply voltage and the ambient temperature). Therefore, in order to obtain the optimal margin, it is desirable that, after the LSI chip is mounted on the circuit board of an apparatus and the apparatus is realized, the output voltage of the output buffer be adjusted when an initial test is conducted or every time the apparatus is started and, thus, the output voltage be set to the optimal value.    [Patent Document 1] Japanese Laid-open Patent Publication No. 11-017518    [Patent Document 2] Japanese Laid-open Patent Publication No. 2006-060751    [Patent Document 3] Japanese Laid-open Patent Publication No. 2007-036546